Software

01: Hardware-Aware Software Optimization

Hardware-aware optimization isn’t a theoretical exercise—it is the absolute difference between a 10x and a 100x computational speedup on real silicon. When handling heavy spatial data streams, traditional application code treats memory as infinite and uniform, which destroys processing efficiency at the hardware level. This research attacks the memory layout problem directly by restructuring 3D spatial arrays to match cache line boundaries, drastically mitigating CPU stall cycles during high-throughput LiDAR transformations.

Note: This work is part of my active summer 2026 research pipeline. Fully validated memory layout architecture diagrams mapping directly to microarchitectural cache hierarchies will go live here as milestones hit ahead of my August 2026 publication deadline.

02: Parallel Exploitation

Modern AI frameworks often obscure the underlying compute layer, but true systems engineering requires mapping dense mathematical graphs directly onto parallel hardware execution lanes. Accelerating multi-dimensional point clouds efficiently means bypassing high-level abstractions to speak directly to the instruction set architecture (ISA). This project utilizes custom assembly and RISC-V Vector configuration registers to achieve massive data parallelism, leveraging strided memory accesses to compute multiple coordinate points simultaneously.

Note: This implementation is actively being ported to bare-metal instruction sets. Syntax-highlighted .s vector assembly snippets and execution lane allocation models are rolling out inline by August 2026.

03: Reproducible Proof & Validation

In systems architecture, performance claims are entirely meaningless without rigorous, deterministic validation that a reviewer can independently verify. Real-world execution times fluctuate based on unrelated OS noise, which is why a credible systems portfolio requires an immutable benchmarking sandbox. This evaluation framework runs inside a containerized QEMU emulation environment, stripping away host anomalies to output absolute, reproducible hardware metrics.

Note: The validation infrastructure is being refined alongside the core vector pipeline. A fully open-source Dockerfile, QEMU deployment scripts, and deterministic clock-cycle profiling logs will be accessible here by August 2026.